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第三章 习题：
改错题（说明原因）： 1.
library ieee; use
ieee.std_logic_1164.all; entity
d_flip_flop is
port(d, clk: in std_logic; q:
out std_logic); end
d_flip_flop; architecture
rtl of d_flip_flop is begin
if clk’event and clk=’1’ then
q<=d;
end if; end
rtl; 2.
library ieee; use
ieee.std_logic_1164.all; entity
d_latch is
port(d, ena: in std_logic; q:
out std_logic); end
d_latch; architecture
rtl of d_latch is begin
if ena = ’1’ then
q<=d;
end if; end
rtl; 3.
library
ieee; use
ieee.std_logic_1164.all; entity
test is
port(d, clk: in std_logic; q:
out std_logic); end
test; architecture
rtl of test is begin
process(clk)
begin
wait until clk’event and clk=’1’
q<=d;
end process; end
rtl; 4.
library ieee; use
ieee.std_logic_1164.all; entity
test is
port(d1, d2: in std_logic; sel:
in std_logic; q:
out std_logic); end
test; architecture
rtl of test is begin
process(d1, d2, sel)
begin
case sel is
when ‘0’ => q <= d1;
when ‘1’ => q <= d2;
end case;
end process; end
rtl; 5.
library ieee; use
ieee.std_logic_1164.all; entity
test is
port(d1, d2: in std_logic; sel:
in std_logic; q:
out std_logic); end
test; architecture
rtl of test is begin
process(d1, d2, sel)
begin
q<=d1 when sel = ’0’ else
d2;
end process; end
rtl; 6.
library ieee; use
ieee.std_logic_1164.all; entity
test is
port(clk: in std_logic; count:
out std_logic_vector(3 downto 0)); end
test; architecture
rtl of test is begin
if clk’event and clk=’1’ then
count<=count+1;
end if; end
rtl; 7.
library ieee; use
ieee.std_logic_1164.all; entity
test is
port(d1, d2: in std_logic; q:
out std_logic); end
test; architecture
rtl of test is begin
process(d1, d2)
signal temp: std_logic;
begin
temp<=d1 and d2;
q<=temp;
end process; end
rtl; 8.
library ieee; use
ieee.std_logic_1164.all; entity
test is
port(clk, a, b: in std_logic; q:
out std_logic); end
test; architecture
rtl of test is begin
process(clk)
begin
if clk’event and clk=’1’ then
q<=a;
else
q<=b;
end if;
end process; end
rtl; 9.
library ieee; use
ieee.std_logic_1164.all; entity
tristate is
port(en, din : in std_logic; dout
: out std_logic); end
tristate; architecture
rtl tristate is begin
process(en, din)
begin
if en=’1’ then
dout<=din;
else
dout<=’z’;
end if;
end process; end
rtl;
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